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http://d-bug.mooo.com/dbugforums/cgi-bin/yabb2/YaBB.pl?num=1362997719 Message started by ggn on 11.03.13 at 10:28:38 |
Title: Yacht (Yet Another Cycle Hunting Table) Post by ggn on 11.03.13 at 10:28:38
Found this document on Atari Forum, on a thread I can't remember. Hope the author doesn't mind the repost!
Yacht (Yet Another Cycle Hunting Table) ------------------------------------------------------------------------------- Forewords : ------------------------------------------------------------------------------- This document is dedicated to the Atari scene for all the past, current and futur good times. This document is based on : - 9th Edition of M68000 8-16-32-bit Microporcessor User's Manual (Motorola, 1993) (laterly refered as M68000UM) - Programmer's Reference Manual Rev 1 (Motorola, 1992) (laterly refered as M68000PRM) - US Patent n°4,325,121 - Two level control store for microprogrammed data processor (Motorola, Apr, 13, 1982) (lately refered as USP4325121) ------------------------------------------------------------------------------- Vocabulary : ------------------------------------------------------------------------------- Clock Cycle : time between two adjacent pulses of the oscillator that sets the tempo of the processor. Microcycle : indivisible CPU cycle of execution : takes 2 clock cycles. Bus Cycle : exept from the Read-Modify-Write Cycle that is only used by the TAS instruction, a bus cycle consists of eight states. Each state longs half a clock cycle so a full bus cycle is 4 clock cycles long. ------------------------------------------------------------------------------- Rules of thumb : ------------------------------------------------------------------------------- 1) 68000 external data bus is 16 bit so any operation on a long word in memory will take at least 2 full bus cycles. 2) 68000 internal data bus is 32 bit so reading/writing word or long word from / to a register take the same time. 3) There are 3 math units. One 16 bit ALU and two 16 bit Address Units. The ALU was complex enough for the math instruction set while the AUs were only able to do address related math (add, subtract). So, The ALU is used in the execution of instructions whereas the AUs are used to calculate the effective address(es). And, of course, the 2 16 bit AUs worked together to make the 32 bit effective address calculations. Therefore, to do a simple 16 bit math instruction, the ALU can do the operation while the AUs perform address calculations during the same micro-cycle. 3a) 68000 ALU is 16 bits so any arithmetic or logic operation between 2 values take more cycles with long words values than with words values even if source and destination are registers. 3b) For arithmetic operations on an address register such as ADDA and SUBA, the whole 32 bits destination address register is used regardless of the operation size (.W or .L). As this arithmetic operation is done by the ALU and no the AUs and in regard of the previous rule (3a), the ALU will take longer to perform word sized operations on address registers than on data registers. 4a) in general case, the source operand is evaluated first then the destination operand is evaluated and, at last, the instruction is executed. These 3 steps can't be mixed. "addi.w #<data>,-(An)" is a good exemple for this rule. 4b) there are some optimized instructions for which the previous rule doesn't apply, destination operand evaluation starts before the end of source operand evaluation. "abcd.b -(Ay),-(Ax)" is a good exemple for this rule. ------------------------------------------------------------------------------- How to read the table : ------------------------------------------------------------------------------- Exec Time : ----------- This table use the same rules than the M68000UM for the exec times. So, data is shown as : n(r/w) where: n is the total number of clock periods r is the number of read cycles w is the number of write cycles. In addition, each exec time is spltted in two parts (when possible) : "instruction exec time" and "effective address exec time". The two exec times must be added in order to get the "real" exec time. Data Bus Usage : ---------------- Each following caracter describe the state of the data bus during a microcycle. n : nop : data bus is not used n- : nop with idle wait, no transfers occur during this microcycle (can last 2 microcycles instead of one ?). p : Program fetch; read from next consecutive location in program memory W : Write MSW onto data bus when using long word w : Write one word onto data bus (LSW if long word operation) R : Read MSW from data bus when using long word r : Read one word from data bus (LSW if long word operation) S : Push (write) MSW onto stack when using long word s : Push (write) one word onto stack (LSW if long word operation) U : Pop (read) MSW from stack when using long word u : Pop (read) one word from stack (LSW if long word operation) V : Fetch vector MSW (for exceptions) v : Fetch vector LSW (for exceptions) i : Vector number acquisition in an IACK Cycle (for Interrupt exception) F : Fetch SSP MSW (for /RESET exception) f : Fetch SSP LSW (for /RESET exception) DON'T TAKE CARE OF SPACES OR PIPES. Exemples : ---------- Note : in the following exemples 'n' caracter will be replace by '.' when the data bus is not used 1) MOVE.W -(An),Dn (line #347) : Takes 10 clock cycles (data bus read 2 times, written 0 times) Data bus usage : ..r.p 2) EORI.L #<data>,-(An) (line #179) : Takes 30 clock cycles (data bus read 5 times, written 2 times) Data bus usage : .p.p..R.r.p.w.W ******************************************************************************* OPERAND EFFECTIVE ADDRESS CALCULATION TIMES ******************************************************************************* ------------------------------------------------------------------------------- <ea> | Exec Time | Data Bus Usage ------------------+-----------------+------------------------------------------ .B or .W : | | Dn | 0(0/0) | An | 0(0/0) | (An) | 4(1/0) | nr (An)+ | 4(1/0) | nr -(An) | 6(1/0) | n nr (d16,An) | 8(2/0) | np nr (d8,An,Xn) | 10(2/0) | n np nr (xxx).W | 8(2/0) | np nr (xxx).L | 12(3/0) | np np nr #<data> | 4(1/0) | np .L : | | Dn | 0(0/0) | An | 0(0/0) | (An) | 8(2/0) | nR nr (An)+ | 8(2/0) | nR nr -(An) | 10(2/0) | n nR nr (d16,An) | 12(3/0) | np nR nr (d8,An,Xn) | 14(3/0) | n np nR nr (xxx).W | 12(3/0) | np nR nr (xxx).L | 16(4/0) | np np nR nr #<data> | 8(2/0) | np np ******************************************************************************* Line 0000 : ADDI, ANDI, ANDI to CCR, BCHG, BCLR, BSET, BTST, CMPI, EORI, EORI to CCR, MOVEP, ORI, ORI to CCR, SUBI ******************************************************************************* ------------------------------------------------------------------------------- EORI, ORI, ANDI, | Exec Time | Data Bus Usage SUBI, ADDI | INSTR EA | 1st Operand | 2nd OP (ea) | INSTR ------------------+-----------------+-------------+---------------+------------ #<data>,<ea> : | | | | .B or .W : | | | | Dn | 8(2/0) 0(0/0) | np | | np (An) | 12(2/1) 4(1/0) | np | nr | np nw (An)+ | 12(2/1) 4(1/0) | np | nr | np nw -(An) | 12(2/1) 6(1/0) | np | n nr | np nw (d16,An) | 12(2/1) 8(2/0) | np | np nr | np nw (d8,An,Xn) | 12(2/1) 10(2/0) | np | n np nr | np nw (xxx).W | 12(2/1) 8(2/0) | np | np nr | np nw (xxx).L | 12(2/1) 12(3/0) | np | np np nr | np nw .L : | | | Dn | 16(3/0) 0(0/0) | np np | | np nn (An) | 20(3/2) 8(2/0) | np np | nR nr | np nw nW (An)+ | 20(3/2) 8(2/0) | np np | nR nr | np nw nW -(An) | 20(3/2) 10(2/0) | np np | n nR nr | np nw nW (d16,An) | 20(3/2) 12(3/0) | np np | np nR nr | np nw nW (d8,An,Xn) | 20(3/2) 14(3/0) | np np | n np nR nr | np nw nW (xxx).W | 20(3/2) 12(3/0) | np np | np nR nr | np nw nW (xxx).L | 20(3/2) 16(4/0) | np np | np np nR nr | np nw nW NOTES : .M68000UM is probably wrong with instruction timming for ANDI.L #<data>,Dn instruction. It reads "14(3/0)" but, according to USP4325121, this instruction is based on the same microwords than EORI.L #<data>,Dn and ORI.L #<data>,Dn that have a "16(3/0)" timming. In addition, evaluation on real hardware confirms the 16 cycles timing. ------------------------------------------------------------------------------- ORI, ANDI, EORI | Exec Time | Data Bus Usage to CCR, to SR | INSTR | 1st Operand | INSTR ------------------+-----------------+-------------+---------------------------- #<data>,CCR | | | .B : | 20(3/0) | np | nn nn np np ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage CMPI | INSTR EA | 1st Operand | 2nd OP (ea) | INSTR ------------------+-----------------+-------------+-------------+-------------- #<data>,<ea> : | | | | .B or .W : | | | | Dn | 8(2/0) 0(0/0) | np | | np (An) | 8(2/0) 4(1/0) | np | nr | np (An)+ | 8(2/0) 4(1/0) | np | nr | np -(An) | 8(2/0) 6(1/0) | np | n nr | np (d16,An) | 8(2/0) 8(2/0) | np | np nr | np (d8,An,Xn) | 8(2/0) 10(2/0) | np | n np nr | np (xxx).W | 8(2/0) 8(2/0) | np | np nr | np (xxx).L | 8(2/0) 12(3/0) | np | np np nr | np .L : | | | | Dn | 14(3/0) 0(0/0) | np np | | np n (An) | 12(3/0) 8(2/0) | np np | nR nr | np (An)+ | 12(3/0) 8(2/0) | np np | nR nr | np -(An) | 12(3/0) 10(2/0) | np np | n nR nr | np (d16,An) | 12(3/0) 12(3/0) | np np | np nR nr | np (d8,An,Xn) | 12(3/0) 14(3/0) | np np | n np nR nr | np (xxx).W | 12(3/0) 12(3/0) | np np | np nR nr | np (xxx).L | 12(3/0) 16(4/0) | np np | np np nR nr | np ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage BCHG, BSET | INSTR EA | 1st Operand | 2nd OP (ea) | INSTR ------------------+-----------------+-------------+---------------+------------ Dn,<ea> : | | | | .B : | | | | (An) | 8(1/1) 4(1/0) | | nr | np nw (An)+ | 8(1/1) 4(1/0) | | nr | np nw -(An) | 8(1/1) 6(1/0) | | n nr | np nw (d16,An) | 8(1/1) 8(2/0) | | np nr | np nw (d8,An,Xn) | 8(1/1) 10(2/0) | | n np nr | np nw (xxx).W | 8(1/1) 8(2/0) | | np nr | np nw (xxx).L | 8(1/1) 12(3/0) | | np np nr | np nw Dn,Dm : | | | | .L : | | | | if Dn<16 | 6(1/0) 0(0/0) | | | np n if Dn>15 | 8(1/0) 0(0/0) | | | np nn #<data>,<ea> : | | | | .B : | | | | (An) | 12(2/1) 4(1/0) | np | nr | np nw (An)+ | 12(2/1) 4(1/0) | np | nr | np nw -(An) | 12(2/1) 6(1/0) | np | n nr | np nw (d16,An) | 12(2/1) 8(2/0) | np | np nr | np nw (d8,An,Xn) | 12(2/1) 10(2/0) | np | n np nr | np nw (xxx).W | 12(2/1) 8(2/0) | np | np nr | np nw (xxx).L | 12(2/1) 12(3/0) | np | np np nr | np nw #<data>,Dn : | | | | .L : | | | | if data<16 | 10(2/0) 0(0/0) | np | | np n if data>15 | 12(2/0) 0(0/0) | np | | np nn ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage BCLR | INSTR EA | 1st Operand | 2nd OP (ea) | INSTR ------------------+-----------------+-------------+---------------+------------ Dn,<ea> : | | | | .B : | | | | (An) | 8(1/1) 4(1/0) | | nr | np nw (An)+ | 8(1/1) 4(1/0) | | nr | np nw -(An) | 8(1/1) 6(1/0) | | n nr | np nw (d16,An) | 8(1/1) 8(2/0) | | np nr | np nw (d8,An,Xn) | 8(1/1) 10(2/0) | | n np nr | np nw (xxx).W | 8(1/1) 8(2/0) | | np nr | np nw (xxx).L | 8(1/1) 12(3/0) | | np np nr | np nw Dn,Dm : | | | | .L : | | | | if Dn<16 | 8(1/0) 0(0/0) | | | np nn if Dn>15 | 10(1/0) 0(0/0) | | | np nn n #<data>,<ea> : | | | | .B : | | | | (An) | 12(2/1) 4(1/0) | np | nr | np nw (An)+ | 12(2/1) 4(1/0) | np | nr | np nw -(An) | 12(2/1) 6(1/0) | np | n nr | np nw (d16,An) | 12(2/1) 8(2/0) | np | np nr | np nw (d8,An,Xn) | 12(2/1) 10(2/0) | np | n np nr | np nw (xxx).W | 12(2/1) 8(2/0) | np | np nr | np nw (xxx).L | 12(2/1) 12(3/0) | np | np np nr | np nw #<data>,Dn : | | | | .L : | | | | if data<16 | 12(2/0) 0(0/0) | np | | np nn if data>15 | 14(2/0) 0(0/0) | np | | np nn n ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage BTST | INSTR EA | 1st Operand | 2nd OP (ea) | INSTR ------------------+-----------------+-------------+---------------+------------ Dn,<ea> : | | | | .B : | | | | (An) | 4(1/0) 4(1/0) | | nr | np (An)+ | 4(1/0) 4(1/0) | | nr | np -(An) | 4(1/0) 6(1/0) | | n nr | np (d16,An) | 4(1/0) 8(2/0) | | np nr | np (d8,An,Xn) | 4(1/0) 10(2/0) | | n np nr | np (xxx).W | 4(1/0) 8(2/0) | | np nr | np (xxx).L | 4(1/0) 12(3/0) | | np np nr | np Dn,Dm : | | | | .L : | 6(1/0) 0(0/0) | | | np n #<data>,<ea> : | | | | .B : | | | | (An) | 8(2/0) 4(1/0) | np | nr | np (An)+ | 8(2/0) 4(1/0) | np | nr | np -(An) | 8(2/0) 6(1/0) | np | n nr | np (d16,An) | 8(2/0) 8(2/0) | np | np nr | np (d8,An,Xn) | 8(2/0) 10(2/0) | np | n np nr | np (xxx).W | 8(2/0) 8(2/0) | np | np nr | np (xxx).L | 8(2/0) 12(3/0) | np | np np nr | np #<data>,Dn : | | | | .L : | 10(2/0) 0(0/0) | np | | np n ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage MOVEP | INSTR | INSTR ------------------+-----------------+------------------------------------------ Dx,(d16,Ay) : | | .W : | 16(2/2) | np nW nw np .L : | 24(2/4) | np nW nW nw nw np (d16,Ay),Dx : | | .W : | 16(4/0) | np nR nr np .L : | 24(6/0) | np nR nR nr nr np NOTES : .Read and write operations are done from the MSB to the LSB on 2 words if using ".w" (first read/write word at Ay+d16 then word at Ay+d16+2)and on 4 words if using ".l" (first read/write word at Ay+d16 then word at Ay+d16+2 then word at Ay+d16+4 and finally word at Ay+d16+6). ******************************************************************************* Line 0001 & Line 0010 & Line 0011 MOVE.B MOVE.L, MOVEA.L MOVE.W, MOVEA.W ******************************************************************************* ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage MOVE | INSTR | 1st OP (ea) | INSTR ------------------+-----------------+---------------+-------------------------- <ea>,Dn : | | | .B or .W : | | | Dn | 4(1/0) | | np An | 4(1/0) | | np (An) | 8(2/0) | nr | np (An)+ | 8(2/0) | nr | np -(An) | 10(2/0) | n nr | np (d16,An) | 12(3/0) | np nr | np (d8,An,Xn) | 14(3/0) | n np nr | np (xxx).W | 12(3/0) | np nr | np (xxx).L | 16(4/0) | np np nr | np #<data> | 8(2/0) | np | np .L : | | | Dn | 4(1/0) | | np An | 4(1/0) | | np (An) | 12(3/0) | nR nr | np (An)+ | 12(3/0) | nR nr | np -(An) | 14(3/0) | n nR nr | np (d16,An) | 16(4/0) | np nR nr | np (d8,An,Xn) | 18(4/0) | n np nR nr | np (xxx).W | 16(4/0) | np nR nr | np (xxx).L | 20(5/0) | np np nR nr | np #<data> | 12(3/0) | np np | np <ea>,(An) : | | | .B or .W : | | | Dn | 8(1/1) | | nw np An | 8(1/1) | | nw np (An) | 12(2/1) | nr | nw np (An)+ | 12(2/1) | nr | nw np -(An) | 14(2/1) | n nr | nw np (d16,An) | 16(3/1) | np nr | nw np (d8,An,Xn) | 18(3/1) | n np nr | nw np (xxx).W | 16(3/1) | np nr | nw np (xxx).L | 20(4/1) | np np nr | nw np #<data> | 12(2/1) | np | nw np .L : | | | Dn | 12(1/2) | | nW nw np An | 12(1/2) | | nW nw np (An) | 20(3/2) | nR nr | nW nw np (An)+ | 20(3/2) | nR nr | nW nw np -(An) | 22(3/2) | n nR nr | nW nw np (d16,An) | 24(4/2) | np nR nr | nW nw np (d8,An,Xn) | 26(4/2) | n np nR nr | nW nw np (xxx).W | 24(4/2) | np nR nr | nW nw np (xxx).L | 28(5/2) | np np nR nr | nW nw np #<data> | 20(3/2) | np np | nW nw np <ea>,(An)+ : | | | .B or .W : | | | Dn | 8(1/1) | | nw np An | 8(1/1) | | nw np (An) | 12(2/1) | nr | nw np (An)+ | 12(2/1) | nr | nw np -(An) | 14(2/1) | n nr | nw np (d16,An) | 16(3/1) | np nr | nw np (d8,An,Xn) | 18(3/1) | n np nr | nw np (xxx).W | 16(3/1) | np nr | nw np (xxx).L | 20(4/1) | np np nr | nw np #<data> | 12(2/1) | np | nw np .L : | | | Dn | 12(1/2) | | nW nw np An | 12(1/2) | | nW nw np (An) | 20(3/2) | nR nr | nW nw np (An)+ | 20(3/2) | nR nr | nW nw np -(An) | 22(3/2) | n nR nr | nW nw np (d16,An) | 24(4/2) | np nR nr | nW nw np (d8,An,Xn) | 26(4/2) | n np nR nr | nW nw np (xxx).W | 24(4/2) | np nR nr | nW nw np (xxx).L | 28(5/2) | np np nR nr | nW nw np #<data> | 20(3/2) | np np | nW nw np <ea>,-(An) : | | | .B or .W : | | | Dn | 8(1/1) | | np nw An | 8(1/1) | | np nw (An) | 12(2/1) | nr | np nw (An)+ | 12(2/1) | nr | np nw -(An) | 14(2/1) | n nr | np nw (d16,An) | 16(3/1) | np nr | np nw (d8,An,Xn) | 18(3/1) | n np nr | np nw (xxx).W | 16(3/1) | np nr | np nw (xxx).L | 20(4/1) | np np nr | np nw #<data> | 12(2/1) | np | np nw .L : | | | Dn | 12(1/2) | | np nw nW An | 12(1/2) | | np nw nW (An) | 20(3/2) | nR nr | np nw nW (An)+ | 20(3/2) | nR nr | np nw nW -(An) | 22(3/2) | n nR nr | np nw nW (d16,An) | 24(4/2) | np nR nr | np nw nW (d8,An,Xn) | 26(4/2) | n np nR nr | np nw nW (xxx).W | 24(4/2) | np nR nr | np nw nW (xxx).L | 28(5/2) | np np nR nr | np nw nW #<data> | 20(3/2) | np np | np nw nW <ea>,(d16,An) : | | | .B or .W : | | | Dn | 12(2/1) | | np nw np An | 12(2/1) | | np nw np (An) | 16(3/1) | nr | np nw np (An)+ | 16(3/1) | nr | np nw np -(An) | 18(3/1) | n nr | np nw np (d16,An) | 20(4/1) | np nr | np nw np (d8,An,Xn) | 22(4/1) | n np nr | np nw np (xxx).W | 20(4/1) | np nr | np nw np (xxx).L | 24(5/1) | np np nr | np nw np #<data> | 16(3/1) | np | np nw np .L : | | | Dn | 16(2/2) | | np nW nw np An | 16(2/2) | | np nW nw np (An) | 24(4/2) | nR nr | np nW nw np (An)+ | 24(4/2) | nR nr | np nW nw np -(An) | 26(4/2) | n nR nr | np nW nw np (d16,An) | 28(5/2) | np nR nr | np nW nw np (d8,An,Xn) | 30(5/2) | n np nR nr | np nW nw np (xxx).W | 28(5/2) | np nR nr | np nW nw np (xxx).L | 32(6/2) | np np nR nr | np nW nw np #<data> | 24(4/2) | np np | np nW nw np <ea>,(d8,An,Xn) : | | | .B or .W : | | | Dn | 14(2/1) | | n np nw np An | 14(2/1) | | n np nw np (An) | 18(3/1) | nr | n np nw np (An)+ | 18(3/1) | nr | n np nw np -(An) | 20(3/1) | n nr | n np nw np (d16,An) | 22(4/1) | np nr | n np nw np (d8,An,Xn) | 24(4/1) | n np nr | n np nw np (xxx).W | 22(4/1) | np nr | n np nw np (xxx).L | 26(5/1) | np np nr | n np nw np #<data> | 18(3/1) | np | n np nw np .L : | | | Dn | 18(2/2) | | n np nW nw np An | 18(2/2) | | n np nW nw np (An) | 26(4/2) | nR nr | n np nW nw np (An)+ | 26(4/2) | nR nr | n np nW nw np -(An) | 28(4/2) | n nR nr | n np nW nw np (d16,An) | 30(5/2) | np nR nr | n np nW nw np (d8,An,Xn) | 32(5/2) | n np nR nr | n np nW nw np (xxx).W | 30(5/2) | np nR nr | n np nW nw np (xxx).L | 34(6/2) | np np nR nr | n np nW nw np #<data> | 26(4/2) | np np | n np nW nw np <ea>,(xxx).W : | | | .B or .W : | | | Dn | 12(2/1) | | np nw np An | 12(2/1) | | np nw np (An) | 16(3/1) | nr | np nw np (An)+ | 16(3/1) | nr | np nw np -(An) | 18(3/1) | n nr | np nw np (d16,An) | 20(4/1) | np nr | np nw np (d8,An,Xn) | 22(4/1) | n np nr | np nw np (xxx).W | 20(4/1) | np nr | np nw np (xxx).L | 24(5/1) | np np nr | np nw np #<data> | 16(3/1) | np | np nw np .L : | | | Dn | 16(2/2) | | np nW nw np An | 16(2/2) | | np nW nw np (An) | 24(4/2) | nR nr | np nW nw np (An)+ | 24(4/2) | nR nr | np nW nw np -(An) | 26(4/2) | n nR nr | np nW nw np (d16,An) | 28(5/2) | np nR nr | np nW nw np (d8,An,Xn) | 30(5/2) | n np nR nr | np nW nw np (xxx).W | 28(5/2) | np nR nr | np nW nw np (xxx).L | 32(6/2) | np np nR nr | np nW nw np #<data> | 24(4/2) | np np | np nW nw np <ea>,(xxx).L : | | | .B or .W : | | | Dn | 16(3/1) | | np np nw np An | 16(3/1) | | np np nw np (An) | 20(4/1) | nr | np nw np np (An)+ | 20(4/1) | nr | np nw np np -(An) | 22(4/1) | n nr | np nw np np (d16,An) | 24(5/1) | np nr | np nw np np (d8,An,Xn) | 26(5/1) | n np nr | np nw np np (xxx).W | 24(5/1) | np nr | np nw np np (xxx).L | 28(6/1) | np np nr | np nw np np #<data> | 20(4/1) | np | np np nw np .L : | | | Dn | 20(3/2) | | np np nW nw np An | 20(3/2) | | np np nW nw np (An) | 28(5/2) | nR nr | np nW nw np np (An)+ | 28(5/2) | nR nr | np nW nw np np -(An) | 30(5/2) | n nR nr | np nW nw np np (d16,An) | 32(6/2) | np nR nr | np nW nw np np (d8,An,Xn) | 34(6/2) | n np nR nr | np nW nw np np (xxx).W | 32(6/2) | np nR nr | np nW nw np np (xxx).L | 36(7/2) | np np nR nr | np nW nw np np #<data> | 28(5/2) | np np | np np nW nw np ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage MOVEA | INSTR | 1st OP (ea) | INSTR ------------------+-----------------+---------------+-------------------------- <ea>,An : | | | .W : | | | Dn | 4(1/0) | | np An | 4(1/0) | | np (An) | 8(2/0) | nr | np (An)+ | 8(2/0) | nr | np -(An) | 10(2/0) | n nr | np (d16,An) | 12(3/0) | np nr | np (d8,An,Xn) | 14(3/0) | n np nr | np (xxx).W | 12(3/0) | np nr | np (xxx).L | 16(4/0) | np np nr | np #<data> | 8(2/0) | np | np .L : | | | Dn | 4(1/0) | | np An | 4(1/0) | | np (An) | 12(3/0) | nR nr | np (An)+ | 12(3/0) | nR nr | np -(An) | 14(3/0) | n nR nr | np (d16,An) | 16(4/0) | np nR nr | np (d8,An,Xn) | 18(4/0) | n np nR nr | np (xxx).W | 16(4/0) | np nR nr | np (xxx).L | 20(5/0) | np np nR nr | np #<data> | 12(3/0) | np np | np ******************************************************************************* Line 0100 CHK, CLR, EXT, ILLEGAL, JMP, JSR, LEA , LINK, MV fr/to CCR/SR, MOVEM, NBCD, NEG, NEGX, NOP, NOT, PEA, RTR, RTS, SWAP, STOP, TAS, TRAP, TRAPV, TST, UNLK ******************************************************************************* ------------------------------------------------------------------------------- CLR, | Exec Time | Data Bus Usage NEGX, NEG, NOT | INSTR EA | 1st OP (ea) | INSTR ------------------+-----------------+---------------+-------------------------- <ea> : | | | .B or .W : | | | Dn | 4(1/0) 0(0/0) | | np (An) | 8(1/1) 4(1/0) | nr | np nw (An)+ | 8(1/1) 4(1/0) | nr | np nw -(An) | 8(1/1) 6(1/0) | n nr | np nw (d16,An) | 8(1/1) 8(2/0) | np nr | np nw (d8,An,Xn) | 8(1/1) 10(2/0) | n np nr | np nw (xxx).W | 8(1/1) 8(2/0) | np nr | np nw (xxx).L | 8(1/1) 12(2/0) | np np nr | np nw .L : | | | Dn | 6(1/0) 0(0/0) | | np n (An) | 12(1/2) 8(2/0) | nR nr | np nw nW (An)+ | 12(1/2) 8(2/0) | nR nr | np nw nW -(An) | 12(1/2) 10(2/0) | n nR nr | np nw nW (d16,An) | 12(1/2) 12(3/0) | np nR nr | np nw nW (d8,An,Xn) | 12(1/2) 14(3/0) | n np nR nr | np nw nW (xxx).W | 12(1/2) 12(3/0) | np nR nr | np nw nW (xxx).L | 12(1/2) 16(4/0) | np np nR nr | np nw nW ------------------------------------------------------------------------------- MOVE | Exec Time | Data Bus Usage from SR | INSTR EA | 2nd Op (ea) | INSTR ------------------+-----------------+---------------+-------------------------- SR,<ea> : | | | .W : | | | Dn | 6(1/0) 0(0/0) | | np n (An) | 8(1/1) 4(1/0) | nr | np nw (An)+ | 8(1/1) 4(1/0) | nr | np nw -(An) | 8(1/1) 6(1/0) | n nr | np nw (d16,An) | 8(1/1) 8(2/0) | np nr | np nw (d8,An,Xn) | 8(1/1) 10(2/0) | n np nr | np nw (xxx).W | 8(1/1) 8(2/0) | np nr | np nw (xxx).L | 8(1/1) 12(3/0) | np np nr | np nw ------------------------------------------------------------------------------- MOVE | Exec Time | Data Bus Usage to CCR, to SR | INSTR EA | 1st OP (ea) | INSTR ------------------+-----------------+---------------+-------------------------- <ea>,CCR : | | | .W : | | | Dn | 12(1/0) 0(0/0) | | nn np np (An) | 12(1/0) 4(1/0) | nr | nn np np (An)+ | 12(1/0) 4(1/0) | nr | nn np np -(An) | 12(1/0) 6(1/0) | n nr | nn np np (d16,An) | 12(1/0) 8(2/0) | np nr | nn np np (d8,An,Xn) | 12(1/0) 10(2/0) | n np nr | nn np np (xxx).W | 12(1/0) 8(2/0) | np nr | nn np np (xxx).L | 12(1/0) 12(3/0) | np np nr | nn np np #<data> | 12(1/0) 4(1/0) | np | nn np np ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage NBCD | INSTR | 1st OP (ea) | INSTR ------------------+-----------------+---------------+-------------------------- <ea> : | | | .B : | | | Dn | 6(1/0) 0(0/0) | | np n (An) | 8(1/1) 4(1/0) | nr | np nw (An)+ | 8(1/1) 4(1/0) | nr | np nw -(An) | 8(1/1) 6(1/0) | n nr | np nw (d16,An) | 8(1/1) 8(2/0) | np nr | np nw (d8,An,Xn) | 8(1/1) 10(2/0) | n np nr | np nw (xxx).W | 8(1/1) 8(2/0) | np nr | np nw (xxx).L | 8(1/1) 12(3/0) | np np nr | np nw ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage PEA | INSTR | INSTR ------------------+-----------------+------------------------------------------ <ea> : | | .L : | | (An) | 12(1/2) | np nS ns (d16,An) | 16(2/2) | np np nS ns (d8,An,Xn) | 20(2/2) | n np n np nS ns (xxx).W | 16(2/2) | np nS ns np (xxx).L | 20(3/2) | np np nS ns np ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage SWAP | INSTR | INSTR ------------------+-----------------+------------------------------------------ Dn : | | .W : | 4(1/0) | np ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage MOVEM | INSTR | INSTR ------------------+-----------------+------------------------------------------ M --> R | | .W | | (An) | 12+4m(3+m/0) | np (nr)* nr np (An)+ | 12+4m(3+m/0) | np (nr)* nr np (d16,An) | 16+4m(4+m/0) | np np (nr)* nr np (d8,An,Xn) | 18+4m(4+m/0) | np n np (nr)* nr np (xxx).W | 16+4m(4+m/0) | np np (nr)* nr np (xxx).L | 20+4m(5+m/0) | np np np (nr)* nr np .L | | (An) | 12+8m(3+2m/0) | np nR (nr nR)* np (An)+ | 12+8m(3+2m/0) | np nR (nr nR)* np (d16,An) | 16+8m(4+2m/0) | np np nR (nr nR)* np (d8,An,Xn) | 18+8m(4+2m/0) | np n np nR (nr nR)* np (xxx).W | 16+8m(4+2m/0) | np np nR (nr nR)* np (xxx).L | 20+8m(5+2m/0) | np np np nR (nr nR)* np R --> M | | .W | | (An) | 8+4m(2/m) | np (nw)* np -(An) | 8+4m(2/m) | np (nw)* np (d16,An) | 12+4m(3/m) | np np (nw)* np (d8,An,Xn) | 14+4m(3/m) | np n np (nw)* np (xxx).W | 12+4m(3/m) | np np (nw)* np (xxx).L | 16+4m(4/m) | np np np (nw)* np .L | | (An) | 8+8m(2/2m) | np (nW nw)* np -(An) | 8+8m(2/2m) | np (nw nW)* np (d16,An) | 12+8m(3/2m) | np np (nW nw)* np (d8,An,Xn) | 14+8m(3/2m) | n np np (nW nw)* np (xxx).W | 12+8m(3/2m) | np np (nW nw)* np (xxx).L | 16+8m(4/2m) | np np np (nW nw)* np NOTES : .'m' is the number of registers to move. .'(nr)*' should be replaced by m consecutive 'nr' .'(nw)*' should be replaced by m consecutive 'nw' .'(nR nr)*' should be replaced by m consecutive 'nR nr' .'(nW nw)*' (or '(nw nW)*') should be replaced by m consecutive 'nW nw' (or m consecutive 'nw nW'). .In M --> R mode, an extra bus read cycle occurs. This extra access can cause errors (for exemple if occuring beyond the bounds of physical memory). .In M --> R mode, MOVEM.W sign-extends words moved to data registers. ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage EXT | INSTR | 1st Operand | INSTR ------------------+-----------------+---------------+-------------------------- Dn : | | | .W : | 4(1/0) | | np .L : | 4(1/0) | | np ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage TST | INSTR EA | 1st OP (ea) | INSTR ------------------+-----------------+---------------+-------------------------- <ea> : | | | .B or .W : | | | Dn | 4(1/0) 0(0/0) | | np (An) | 4(1/0) 4(1/0) | nr | np (An)+ | 4(1/0) 4(1/0) | nr | np -(An) | 4(1/0) 6(1/0) | n nr | np (d16,An) | 4(1/0) 8(2/0) | np nr | np (d8,An,Xn) | 4(1/0) 10(2/0) | n np nr | np (xxx).W | 4(1/0) 8(2/0) | np nr | np (xxx).L | 4(1/0) 12(3/0) | np np nr | np .L | | | Dn | 4(1/0) 0(0/0) | | np (An) | 4(1/0) 8(2/0) | nR nr | np (An)+ | 4(1/0) 8(2/0) | nR nr | np -(An) | 4(1/0) 10(2/0) | n nR nr | np (d16,An) | 4(1/0) 12(3/0) | np nR nr | np (d8,An,Xn) | 4(1/0) 14(3/0) | n np nR nr | np (xxx).W | 4(1/0) 12(3/0) | np nR nr | np (xxx).L | 4(1/0) 16(4/0) | np np nR nr | np ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage TAS | INSTR EA | 1st OP (ea) | INSTR ------------------+-----------------+---------------+-------------------------- <ea> : | | | .B : | | | Dn | 4(1/0) 0(0/0) | | np (An) | 10(1/1) 4(1/0) | nr | n nw np (An)+ | 10(1/1) 4(1/0) | nr | n nw np -(An) | 10(1/1) 6(1/0) | n nr | n nw np (d16,An) | 10(1/1) 8(2/0) | np nr | n nw np (d8,An,Xn) | 10(1/1) 10(2/0) | n np nr | n nw np (xxx).W | 10(1/1) 8(1/0) | | n nw np (xxx).L | 10(1/1) 12(2/0) | | n nw np NOTES : .M68000UM is probably wrong with instruction timming when <ea> is different from Dn. It reads "14(3/0)" but according to the same book the read-modify- write bus cycle used by this instruction is only 10 clock cycles long which seems coherent with the microwords decomposition in USP4325121. Last, evaluation on real hardware confirms the 10 cycles timing. ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage CHK | INSTR EA | 1st OP (ea) | INSTR ------------------+-----------------+---------------+-------------------------- no trap : | | | <ea>,Dn : | | / .W : | | / Dn | 10(1/0) 0(0/0) | | np nn n (An) | 10(1/0) 4(1/0) | nr | np nn n (An)+ | 10(1/0) 4(1/0) | nr | np nn n -(An) | 10(1/0) 6(1/0) | n nr | np nn n (d16,An) | 10(1/0) 8(2/0) | np nr | np nn n (d8,An,Xn) | 10(1/0) 10(2/0) | n np nr | np nn n (xxx).W | 10(1/0) 8(2/0) | np nr | np nn n (xxx).L | 10(1/0) 12(2/0) | np np nr | np nn n #<data> | 10(1/0) 4(1/0) | np | np nn n trap : | | | <ea>,Dn : | | | .W : | | | Dn > Src : | | | Dn | 38(5/3) 0(0/0) | |np nn ns nS ns np np np np (An) | 38(5/3) 4(1/0) | nr |np nn ns nS ns np np np np (An)+ | 38(5/3) 4(1/0) | nr |np nn ns nS ns np np np np -(An) | 38(5/3) 6(1/0) | n nr |np nn ns nS ns np np np np (d16,An) | 38(5/3) 8(2/0) | np nr |np nn ns nS ns np np np np (d8,An,Xn)| 38(5/3) 10(2/0) | n np nr |np nn ns nS ns np np np np (xxx).W | 38(5/3) 8(2/0) | np nr |np nn ns nS ns np np np np (xxx).L | 38(5/3) 12(2/0) | np np nr |np nn ns nS ns np np np np #<data> | 38(5/3) 4(1/0) | np |np nn ns nS ns np np np np Dn <0 : | | | Dn | 40(5/3) 0(0/0) | |np n- nn ns nS ns np np np np (An) | 40(5/3) 4(1/0) | nr |np n- nn ns nS ns np np np np (An)+ | 40(5/3) 4(1/0) | nr |np n- nn ns nS ns np np np np -(An) | 40(5/3) 6(1/0) | n nr |np n- nn ns nS ns np np np np (d16,An) | 40(5/3) 8(2/0) | np nr |np n- nn ns nS ns np np np np (d8,An,Xn)| 40(5/3) 10(2/0) | n np nr |np n- nn ns nS ns np np np np (xxx).W | 40(5/3) 8(2/0) | np nr |np n- nn ns nS ns np np np np (xxx).L | 40(5/3) 12(2/0) | np np nr |np n- nn ns nS ns np np np np #<data> | 40(5/3) 4(1/0) | np |np n- nn ns nS ns np np np np NOTES : . for more informations about the "trap" lines see exceptions section below. ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage LEA | INSTR | INSTR ------------------+-----------------+------------------------------------------ <ea>,An : | | .L : | | (An) | 4(1/0) | np (d16,An) | 8(2/0) | np np (d8,An,Xn) | 12(2/0) | n np n np (xxx).W | 8(2/0) | np np (xxx).L | 12(3/0) | np np np ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage JSR | INSTR | INSTR ------------------+-----------------+------------------------------------------ <ea> : | | (An) | 16(2/2) | np nS ns np (d16,An) | 18(2/2) | n np nS ns np (d8,An,Xn) | 22(2/2) | n nn np nS ns np (xxx).W | 18(2/2) | n np nS ns np (xxx).L | 20(3/2) | np np nS ns np ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage JMP | INSTR | INSTR ------------------+-----------------+------------------------------------------ <ea> : | | (An) | 8(2/0) | np np (d16,An) | 10(2/0) | n np np (d8,An,Xn) | 14(2/0) | n nn np np (xxx).W | 10(2/0) | n np np (xxx).L | 12(3/0) | np np np NOTES : .M68000UM is probably wrong with bus read accesses for JMP (d8,An,Xn),Dn instruction. It reads "14(3/0)" but, according to USP4325121 and with a little common sense, 2 bus read accesses are far enough. ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage MOVE USP | INSTR | INSTR ------------------+-----------------+------------------------------------------ An,USP : | 4(1/0) | np USP,An : | 4(1/0) | np ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage RESET | INSTR | INSTR ------------------+-----------------+------------------------------------------ | 132(1/0) | nn (??-)* np NOTES : .(??)* is for 124 cycles when the CPU will asserts the /RSTO signal in order to reset all external devices. Normally, the CPU won't use the bus during these cycles. .RESET instruction have nothing to do with /RESET exception. ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage NOP | INSTR | INSTR ------------------+-----------------+------------------------------------------ | 4(1/0) | np ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage STOP | INSTR | INSTR ------------------+-----------------+------------------------------------------ | 4(0/0) | n NOTES : .At this point, there is no real clues of how the second microcyle of this * instruction is spent. ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage RTE, RTR | INSTR | INSTR ------------------+-----------------+------------------------------------------ | 20(5/0) | nU nu nu np np NOTES : .M68000UM is probably wrong with bus read accesses for RTR instruction. It reads "20(2/0)" but, according to USP4325121 and with a little common sense, 2 bus read accesses aren't enough for reading status register and program counter values from the stack and prefetching. ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage RTS | INSTR | INSTR ------------------+-----------------+------------------------------------------ | 16(4/0) | nU nu np np ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage TRAPV | INSTR | INSTR ------------------+-----------------+------------------------------------------ no trap | 4(1/0) | np trap | 34(5/3) | np ns nS ns np np np np NOTES : . for more informations about the "trap" line see exceptions section below. ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage LINK | INSTR | 2nd Operand | INSTR ------------------+-----------------+---------------+-------------------------- An,#<data> : | | .W : | 16(2/2) | np nS ns np ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage UNLNK | INSTR | INSTR ------------------+-----------------+------------------------------------------ An : | 12(3/0) | nU nu np ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage ILLEGAL, TRAP | INSTR | INSTR ------------------+-----------------+------------------------------------------ | 34(4/3) | nn ns nS ns np np np np NOTES : .For more informations about this instruction see exceptions section below. ******************************************************************************* Line 0101 ADDQ, DBcc, Scc, SUBQ ******************************************************************************* ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage ADDQ, SUBQ | INSTR EA | 1st OP (ea) | INSTR ------------------+-----------------+---------------+-------------------------- #<data>,<ea> : | | | .B or .W : | | | Dn | 4(1/0) 0(0/0) | | np An | 8(1/0) 0(0/0) | | np nn (An) | 8(1/1) 4(1/0) | nr | np nw (An)+ | 8(1/1) 4(1/0) | nr | np nw -(An) | 8(1/1) 6(1/0) | n nr | np nw (d16,An) | 8(1/1) 8(2/0) | np nr | np nw (d8,An,Xn) | 8(1/1) 10(2/0) | n np nr | np nw (xxx).W | 8(1/1) 8(2/0) | np nr | np nw (xxx).L | 8(1/1) 12(3/0) | np np nr | np nw .L : | | | Dn | 8(1/0) 0(0/0) | | np nn An | 8(1/0) 0(0/0) | | np nn (An) | 12(1/2) 8(2/0) | nR nr | np nw nW (An)+ | 12(1/2) 8(2/0) | nR nr | np nw nW -(An) | 12(1/2) 10(2/0) | n nR nr | np nw nW (d16,An) | 12(1/2) 12(3/0) | np nR nr | np nw nW (d8,An,Xn) | 12(1/2) 14(3/0) | n np nR nr | np nw nW (xxx).W | 12(1/2) 12(3/0) | np nR nr | np nw nW (xxx).L | 12(1/2) 16(4/0) | np np nR nr | np nw nW NOTES : .M68000UM is probably wrong with instruction timing for ADDQ.W #<data>,An instruction. It reads "4(1/0)" but, according to USP4325121, this instruction is based on the same microwords than ADDQ.L #<data>,Dn and ADDQ.L #<data>,An that have a "8(3/0)" timing. That makes sense because of the calculation of a 32 bit address on 16 bits ALU. In addition, evaluation on real hardware confirms the 8 cycles timing and, last, it makes addq and subbq coherent in term of timing. ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage DBcc | INSTR | INSTR ------------------+-----------------+------------------------------------------ Dn,<label> : | | branch taken | 10(2/0) | n np np branch not taken| | cc true | 12(2/0) | n n np np counter exp | 14(3/0) | n np np np NOTES : .DBcc does not exist in USP4325121. Only does a primitive instruction DCNT tht doesn't succeded to reach the production version of M68000 CPU. Nervertheless, looking at DCNT and Bcc micro/nanowords can lead to a realistic idea of how DBcc should work. At least, this re-enginering of DBcc matches the timing written in M68000UM for this instruction. FLOWCHART : cc n /cc +-------------------+-------------------+ n z np /z | +---------+---------+ +---------------------------->np | | | np<-----------------+ ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage Scc | INSTR EA | 1st OP (ea) | INSTR ------------------+-----------------+---------------+-------------------------- <ea> : | | | .B : | | | cc false | | | Dn | 4(1/0) 0(0/0) | | np (An) | 8(1/1) 4(1/0) | nr | np nw (An)+ | 8(1/1) 4(1/0) | nr | np nw -(An) | 8(1/1) 6(1/0) | n nr | np nw (d16,An) | 8(1/1) 8(2/0) | np nr | np nw (d8,An,Xn) | 8(1/1) 10(2/0) | n np nr | np nw (xxx).W | 8(1/1) 8(2/0) | np nr | np nw (xxx).L | 8(1/1) 12(3/0) | np np nr | np nw cc true | | | Dn | 6(1/0) 0(0/0) | | np n (An) | 8(1/1) 4(1/0) | nr | np nw (An)+ | 8(1/1) 4(1/0) | nr | np nw -(An) | 8(1/1) 6(1/0) | n nr | np nw (d16,An) | 8(1/1) 8(2/0) | np nr | np nw (d8,An,Xn) | 8(1/1) 10(2/0) | n np nr | np nw (xxx).W | 8(1/1) 8(2/0) | np nr | np nw (xxx).L | 8(1/1) 12(3/0) | np np nr | np nw ******************************************************************************* Line 0110 Bcc, BRA, BSR ******************************************************************************* ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage BRA | INSTR | INSTR ------------------+-----------------+------------------------------------------ <label> : | | .B, .S or .W : | 10(2/0) | n np np ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage BSR | INSTR | INSTR ------------------+-----------------+------------------------------------------ <label> : | | .B .S or .W : | 18(2/2) | n nS ns np np ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage Bcc | INSTR | INSTR ------------------+-----------------+------------------------------------------ <label> : | | .B or .S : | | branch taken | 10(2/0) | n np np branch not taken| 8(1/0) | nn np .W : | | branch taken | 10(2/0) | n np np branch not taken| 12(2/0) | nn np np ******************************************************************************* Line 0111 MOVEQ ******************************************************************************* ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage MOVEQ | INSTR | 1st OP (ea) | INSTR ------------------+-----------------+---------------+-------------------------- #<data>,Dn : | | .L : | 4(1/0) | np ******************************************************************************* Line 1000 & Line 1100 DIVS, DIVU, OR, SBCD ABCD, AND, EXG, MULS, MULU ******************************************************************************* ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage ABCD, SBCD | INSTR | INSTR ------------------+-----------------+------------------------------------------ Dy,Dx : | | .B : | 6(1/0) | np n -(Ay),-(Ax) : | | .B : | 18(3/1) | n nr nr np nw ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage AND, OR | INSTR EA | 1st OP (ea) | INSTR ------------------+-----------------+---------------+-------------------------- <ea>,Dn : | | | .B or .W : | | | Dn | 4(1/0) 0(0/0) | | np (An) | 4(1/0) 4(1/0) | nr | np (An)+ | 4(1/0) 4(1/0) | nr | np -(An) | 4(1/0) 6(1/0) | n nr | np (d16,An) | 4(1/0) 8(2/0) | np nr | np (d8,An,Xn) | 4(1/0) 10(2/0) | n np nr | np (xxx).W | 4(1/0) 8(2/0) | np nr | np (xxx).L | 4(1/0) 12(3/0) | np np nr | np #<data> | 4(1/0) 4(1/0) | np | np .L : | | | Dn | 8(1/0) 0(0/0) | | np nn (An) | 6(1/0) 8(2/0) | nR nr | np n (An)+ | 6(1/0) 8(2/0) | nR nr | np n -(An) | 6(1/0) 10(2/0) | n nR nr | np n (d16,An) | 6(1/0) 12(3/0) | np nR nr | np n (d8,An,Xn) | 6(1/0) 14(3/0) | n np nR nr | np n (xxx).W | 6(1/0) 12(3/0) | np nR nr | np n (xxx).L | 6(1/0) 16(4/0) | np np nR nr | np n #<data> | 8(1/0) 8(2/0) | np np | np nn Dn,<ea> : | | | .B or .W : | | | (An) | 8(1/1) 4(1/0) | nr | np nw (An)+ | 8(1/1) 4(1/0) | nr | np nw -(An) | 8(1/1) 6(1/0) | n nr | np nw (d16,An) | 8(1/1) 8(2/0) | np nr | np nw (d8,An,Xn) | 8(1/1) 10(2/0) | n np nr | np nw (xxx).W | 8(1/1) 8(2/0) | np nr | np nw (xxx).L | 8(1/1) 12(3/0) | np np nr | np nw .L : | | (An) | 12(1/2) 8(2/0) | nR nr | np nw nW (An)+ | 12(1/2) 8(2/0) | nR nr | np nw nW -(An) | 12(1/2) 10(2/0) | n nR nr | np nw nW (d16,An) | 12(1/2) 12(3/0) | np nR nr | np nw nW (d8,An,Xn) | 12(1/2) 14(3/0) | n np nR nr | np nw nW (xxx).W | 12(1/2) 12(3/0) | np nR nr | np nw nW (xxx).L | 12(1/2) 16(4/0) | np np nR nr | np nw nW ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage DIVU | INSTR EA | 1st OP (ea) | INSTR ------------------+-----------------+---------------+-------------------------- <ea>,Dn : / | | .W : | | | Dn | 76+?(1/0) 0(0/0) | | nn n [seq.] n nn np (An) | 76+?(1/0) 4(1/0) | nr | nn n [seq.] n nn np (An)+ | 76+?(1/0) 4(1/0) | nr | nn n [seq.] n nn np -(An) | 76+?(1/0) 6(1/0) | n nr | nn n [seq.] n nn np (d16,An) | 76+?(1/0) 8(2/0) | np nr | nn n [seq.] n nn np (d8,An,Xn) | 76+?(1/0) 10(2/0) | n np nr | nn n [seq.] n nn np (xxx).W | 76+?(1/0) 8(2/0) | np nr | nn n [seq.] n nn np (xxx).L | 76+?(1/0) 12(2/0) | np np nr | nn n [seq.] n nn np #<data> | 76+?(1/0) 8(2/0) | np np | nn n [seq.] n nn np NOTES : .Overflow always cost 10 cycles (n nn np). .For more informations about division by zero see exceptions section below. .[seq.] refers to 15 consecutive blocks to be chosen in the following 3 : (nn), (nnn-) or (nnn-n). (see following flowchart for details). .Best case : 76 cycles (nn n [nn]*15 n nn np) .Worst case : 136 (140 ?) cycles. FLOWCHART : n n Divide by zero +--------------------+--------------------+ Overflow n n +-----------+----------+ n np n<---------------------+-+-+ nw n | | | nw No more bits | pMSB=0 pMSB=1 | | | nw +-----+-----+-----------+ | | | np n MSB=0 n- MSB=1 | | | | np np +---+---+ +----+ | | np | n | | np | +--------------+ | +------------------------+ .for each iteration of the loop : shift dividend to the left by 1 bit then substract divisor to the MSW of new dividend, discard after test if result is negative keep it if positive. .MSB = most significant bit : bit at the far left of the dividend .pMSB = previous MSB : MSB used in the previous iteration of the loop ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage DIVS | INSTR EA | 1st OP (ea) | INSTR ------------------+-----------------+---------------+-------------------------- <ea>,Dn : / / / .W : / / / Dn |120+?(1/0) 0(0/0)| | nn nnn (n)n [seq] nnn-nnn n(n(n))np (An) |120+?(1/0) 4(1/0)| nr| nn nnn (n)n [seq] nnn-nnn n(n(n))np (An)+ |120+?(1/0) 4(1/0)| nr| nn nnn (n)n [seq] nnn-nnn n(n(n))np -(An) |120+?(1/0) 6(1/0)|n nr| nn nnn (n)n [seq] nnn-nnn n(n(n))np (d16,An) |120+?(1/0) 8(2/0)| np nr| nn nnn (n)n [seq] nnn-nnn n(n(n))np (d8,An,Xn)|120+?(1/0) 10(2/0)|n np nr| nn nnn (n)n [seq] nnn-nnn n(n(n))np (xxx).W |120+?(1/0) 8(2/0)| np nr| nn nnn (n)n [seq] nnn-nnn n(n(n))np (xxx).L |120+?(1/0) 12(2/0)| np np nr| nn nnn (n)n [seq] nnn-nnn n(n(n))np #<data> |120+?(1/0) 8(2/0)| np np | nn nnn (n)n [seq] nnn-nnn n(n(n))np NOTES : .Overflow cost 16 or 18 cycles depending on dividend sign (n nn nn (n)n np). .For more informations about division by zero see exceptions section below. .[seq.] refers to 15 consecutive blocks to be chosen in the following 2 : (nnn-n) or (nn-n). (see following flowchart for details). .Best case : 120-122 cycles depending on dividend sign. .Worst case : 156 (158 ?) cycles. FLOWCHART : n n Divide by zero +--------+--------------------------------+ n n n n Dividend<0 n Dividend>0 nw +-----+-----+ nw n | nw +---------->n np | Overflow np +-----------------+ +----+----+ np | +----------+ +----->n np np | | +---------->n | | n- | | MSB=1 MSB=0 n No more bits | | +-----------+--------+--------+ | +-+ | n +---------------+ divisor<0 n divisor>0 +----------+-----------+ n dividend<0 n dividend>0 n +----------+----+ np n np n np .for each iteration of the loop : shift quotient to the left by 1 bit. .MSB = most significant bit : bit at the far left of the quotient. ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage EXG | INSTR | INSTR ------------------+-----------------+------------------------------------------ .L : | | Dx,Dy | 6(1/0) | np n Ax,Ay | 6(1/0) | np n Dx,Ay | 6(1/0) | np n ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage MULU,MULS | INSTR EA | 1st OP (ea) | INSTR ------------------+-----------------+---------------+-------------------------- <ea>,Dn : / | | .W : / | | Dn | 38+2m(1/0) 0(0/0) | | np n* (An) | 38+2m(1/0) 4(1/0) | nr | np n* (An)+ | 38+2m(1/0) 4(1/0) | nr | np n* -(An) | 38+2m(1/0) 6(1/0) | n nr | np n* (d16,An) | 38+2m(1/0) 8(2/0) | np nr | np n* (d8,An,Xn) | 38+2m(1/0) 10(2/0) | n np nr | np n* (xxx).W | 38+2m(1/0) 8(2/0) | np nr | np n* (xxx).L | 38+2m(1/0) 12(2/0) | np np nr | np n* #<data> | 38+2m(1/0) 8(2/0) | np np | np n* NOTES : .for MULU 'm' = the number of ones in the source - Best case 38 cycles with $0 - Worst case : 70 cycles with $FFFF .for MULS 'm' = concatenate the 16-bit pointed by <ea> with a zero as the LSB 'm' is the resultant number of 10 or 01 patterns in the 17-bit source. - Best case : 38 cycles with $0 or $FFFF - Worst case : 70 cycles with $5555 .in both cases : 'n*' should be replaced by 17+m consecutive 'n' FLOWCHART : np LSB=1 | LSB=0 +------------+------------+ | | +->n------------------------>n<----+ | | | LSB=0 or | No more bits | | 2LSB=00,11 LSB=1 or +---------------+------------+-----+ 2LSB=01,10 | n .LSB = less significant bit : bit at the far right of the source. .2LSB = 2 less significant bits : 2 last bits at the far right of the source. ******************************************************************************* Line 1001 & Line 1101 SUB, SUBA, SUBX ADD, ADDA, ADDX ******************************************************************************* ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage ADD, SUB | INSTR EA | 1st Operand | 2nd OP (ea) | INSTR ------------------+-----------------+-------------+---------------+------------ <ea>,Dn : | | \ | .B or .W : | | | | Dn | 4(1/0) 0(0/0) | | | np An | 4(1/0) 0(0/0) | | | np (An) | 4(1/0) 4(1/0) | nr | | np (An)+ | 4(1/0) 4(1/0) | nr | | np -(An) | 4(1/0) 6(1/0) | n nr | | np (d16,An) | 4(1/0) 8(2/0) | np nr | | np (d8,An,Xn) | 4(1/0) 10(2/0) | n np nr | | np (xxx).W | 4(1/0) 8(2/0) | np nr | | np (xxx).L | 4(1/0) 12(3/0) | np np nr | | np #<data> | 4(1/0) 4(1/0) np | np .L : | | | | Dn | 8(1/0) 0(0/0) | | | np nn An | 8(1/0) 0(0/0) | | | np nn (An) | 6(1/0) 8(2/0) | nR nr | | np n (An)+ | 6(1/0) 8(2/0) | nR nr | | np n -(An) | 6(1/0) 10(2/0) | n nR nr | | np n (d16,An) | 6(1/0) 12(3/0) | np nR nr | | np n (d8,An,Xn) | 6(1/0) 14(3/0) | n np nR nr | | np n (xxx).W | 6(1/0) 12(3/0) | np nR nr | | np n (xxx).L | 6(1/0) 16(4/0) | np np nR nr | | np n #<data> | 8(1/0) 8(2/0) | np np | np nn Dn,<ea> : | | / | .B or .W : | | | | (An) | 8(1/1) 4(1/0) | | nr | np nw (An)+ | 8(1/1) 4(1/0) | | nr | np nw -(An) | 8(1/1) 6(1/0) | | n nr | np nw (d16,An) | 8(1/1) 8(2/0) | | np nr | np nw (d8,An,Xn) | 8(1/1) 10(2/0) | | n np nr | np nw (xxx).W | 8(1/1) 8(2/0) | | np nr | np nw (xxx).L | 8(1/1) 12(3/0) | | np np nr | np nw .L : | | | | (An) | 12(1/2) 8(2/0) | | nr | np nw nW (An)+ | 12(1/2) 8(2/0) | | nr | np nw nW -(An) | 12(1/2) 10(2/0) | | n nR nr | np nw nW (d16,An) | 12(1/2) 12(3/0) | | np nR nr | np nw nW (d8,An,Xn) | 12(1/2) 14(3/0) | | n np nR nr | np nw nW (xxx).W | 12(1/2) 12(3/0) | | np nR nr | np nw nW (xxx).L | 12(1/2) 16(4/0) | | np np nR nr | np nw nW ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage ADDA, SUBA | INSTR EA | 1st OP (ea) | INSTR ------------------+-----------------+---------------+-------------------------- <ea>,An : | | | .B or .W : | | | Dn | 8(1/0) 0(0/0) | | np nn An | 8(1/0) 0(0/0) | | np nn (An) | 8(1/0) 4(1/0) | nr | np nn (An)+ | 8(1/0) 4(1/0) | nr | np nn -(An) | 8(1/0) 6(1/0) | n nr | np nn (d16,An) | 8(1/0) 8(2/0) | np nr | np nn (d8,An,Xn) | 8(1/0) 10(2/0) | n np nr | np nn (xxx).W | 8(1/0) 8(2/0) | np nr | np nn (xxx).L | 8(1/0) 12(3/0) | np np nr | np nn #<data> | 8(1/0) 4(1/0) | np | np nn .L : | | | Dn | 8(1/0) 0(0/0) | | np nn An | 8(1/0) 0(0/0) | | np nn (An) | 6(1/0) 8(2/0) | nR nr | np n (An)+ | 6(1/0) 8(2/0) | nR nr | np n -(An) | 6(1/0) 10(2/0) | n nR nr | np n (d16,An) | 6(1/0) 12(3/0) | np nR nr | np n (d8,An,Xn) | 6(1/0) 14(3/0) | n np nR nr | np n (xxx).W | 6(1/0) 12(3/0) | np nR nr | np n (xxx).L | 6(1/0) 16(4/0) | np np nR nr | np n #<data> | 8(1/0) 8(2/0) | np np | np nn ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage ADDX, SUBX | INSTR | INSTR ------------------+-----------------+------------------------------------------ Dy,Dx : | | .B or .W : | 4(1/0) | np .L : | 8(1/0) | np nn -(Ay),-(Ax) : | | .B or .W : | 18(3/1) | n nr nr np nw .L : | 30(5/2) | n nr nR nr nR nw np nW ******************************************************************************* Line 1010 Reserved ******************************************************************************* ******************************************************************************* Line 1011 CMP, CMPA, CMPM, EOR ******************************************************************************* ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage CMP | INSTR EA | 1st OP (ea) | INSTR ------------------+-----------------+---------------+-------------------------- <ea>,Dn : | | | .B or .W : | | | Dn | 4(1/0) 0(0/0) | | np An | 4(1/0) 0(0/0) | | np (An) | 4(1/0) 4(1/0) | nr | np (An)+ | 4(1/0) 4(1/0) | nr | np -(An) | 4(1/0) 6(1/0) | n nr | np (d16,An) | 4(1/0) 8(2/0) | np nr | np (d8,An,Xn) | 4(1/0) 10(2/0) | n np nr | np (xxx).W | 4(1/0) 8(2/0) | np nr | np (xxx).L | 4(1/0) 12(3/0) | np np nr | np #<data> | 4(1/0) 4(1/0) | np | np .L : | | | Dn | 6(1/0) 0(0/0) | | np n An | 6(1/0) 0(0/0) | | np n (An) | 6(1/0) 8(1/0) | nR nr | np n (An)+ | 6(1/0) 8(1/0) | nR nr | np n -(An) | 6(1/0) 10(1/0) | n nR nr | np n (d16,An) | 6(1/0) 12(2/0) | np nR nr | np n (d8,An,Xn) | 6(1/0) 14(2/0) | n np nR nr | np n (xxx).W | 6(1/0) 12(2/0) | np nR nr | np n (xxx).L | 6(1/0) 16(3/0) | np np nR nr | np n #<data> | 6(1/0) 8(2/0) | np np | np n ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage CMPA | INSTR EA | 1st OP (ea) | INSTR ------------------+-----------------+---------------+-------------------------- <ea>,An : | | | .B or .W : | | | Dn | 6(1/0) 0(0/0) | | np n An | 6(1/0) 0(0/0) | | np n (An) | 6(1/0) 4(1/0) | nr | np n (An)+ | 6(1/0) 4(1/0) | nr | np n -(An) | 6(1/0) 6(1/0) | n nr | np n (d16,An) | 6(1/0) 8(2/0) | np nr | np n (d8,An,Xn) | 6(1/0) 10(2/0) | n np nr | np n (xxx).W | 6(1/0) 8(2/0) | np nr | np n (xxx).L | 6(1/0) 12(3/0) | np np nr | np n #<data> | 6(1/0) 4(1/0) | np | np n .L : | | | Dn | 6(1/0) 0(0/0) | | np n An | 6(1/0) 0(0/0) | | np n (An) | 6(1/0) 8(1/0) | nR nr | np n (An)+ | 6(1/0) 8(1/0) | nR nr | np n -(An) | 6(1/0) 10(1/0) | n nR nr | np n (d16,An) | 6(1/0) 12(2/0) | np nR nr | np n (d8,An,Xn) | 6(1/0) 14(2/0) | n np nR nr | np n (xxx).W | 6(1/0) 12(2/0) | np nR nr | np n (xxx).L | 6(1/0) 16(3/0) | np np nR nr | np n #<data> | 6(1/0) 8(2/0) | np np | np n ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage CMPM | INSTR | INSTR ------------------+-----------------+------------------------------------------ (Ay)+,(Ax)+ | | .B or .W : | 12(3/0) | nr nr np .L : | 20(5/0) | nR nr nR nr np ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage EOR | INSTR EA | 1st OP (ea) | INSTR ------------------+-----------------+---------------+-------------------------- Dn,<ea> : | | | .B or .W : | | | Dn | 4(1/0) 0(0/0) | | np (An) | 8(1/1) 4(1/0) | nr | np nw (An)+ | 8(1/1) 4(1/0) | nr | np nw -(An) | 8(1/1) 6(1/0) | n nr | np nw (d16,An) | 8(1/1) 8(2/0) | np nr | np nw (d8,An,Xn) | 8(1/1) 10(2/0) | n np nr | np nw (xxx).W | 8(1/1) 8(2/0) | np nr | np nw (xxx).L | 8(1/1) 12(3/0) | np np nr | np nw .L : | | | Dn | 8(1/0) 0(0/0) | | np nn (An) | 12(1/2) 8(2/0) | nR nr | np nw nW (An)+ | 12(1/2) 8(2/0) | nR nr | np nw nW -(An) | 12(1/2) 10(2/0) | n nR nr | np nw nW (d16,An) | 12(1/2) 12(3/0) | np nR nr | np nw nW (d8,An,Xn) | 12(1/2) 14(3/0) | n np nR nr | np nw nW (xxx).W | 12(1/2) 12(3/0) | np nR nr | np nw nW (xxx).L | 12(1/2) 16(4/0) | np np nR nr | np nw nW ******************************************************************************* Line 1110 ASL, ASR, LSL, LSR, ROL, ROR, ROXL, ROXR ******************************************************************************* ------------------------------------------------------------------------------- ASL, ASR, | Exec Time | Data Bus Usage LSL, LSR, | | ROL, ROR, | | ROXL, ROXR | INSTR EA | 1st OP (ea) | INSTR ------------------+-----------------+---------------+-------------------------- Dx,Dy : | | | .B or .W : | 6+2m(1/0) | | np n* n .L : | 8+2m(1/0) | | np n* nn #<data>,Dy : | | | .B or .W : | 6+2m(1/0) | | np n n* .L : | 8+2m(1/0) | | np nn n* <ea> : | | | .B or .W : | | | (An) | 8(1/1) 4(1/0) | nr | np nw (An)+ | 8(1/1) 4(1/0) | nr | np nw -(An) | 8(1/1) 6(1/0) | n nr | np nw (d16,An) | 8(1/1) 8(2/0) | np nr | np nw (d8,An) | 8(1/1) 10(2/0) | n np nr | np nw (xxx).W | 8(1/1) 8(2/0) | np nr | np nw (xxx).L | 8(1/1) 12(3/0) | np np nr | np nw NOTES : .'m' is the shift count. .'n*' should be replaced by m consecutive 'n' ******************************************************************************* Line 1111 Reserved ******************************************************************************* ******************************************************************************* EXCEPTION PROCESSING EXECUTION TIMES ******************************************************************************* ------------------------------------------------------------------------------- | Periods | Data Bus Usage ----------------------+----------+--------------------------------------------- | | Group 0 : | | Address error | 50(4/7) | nn ns nS ns ns ns nS ns nV nv np np Bus error | 50(4/7) | nn ns nS ns ns ns nS ns nV nv np np /RESET | 40(6/0) | (n-)*5 nn nF nf nV nv np np Group 1 : | | Trace | 34(4/3) | nn ns nS ns nV nv np np Interrupt | 44(5/3) | n nn ns ni n- n nS ns nV nv np np Privilege Violation | 34(4/3) | nn ns nS ns nV nv np np Illegal Instruction | 34(4/3) | nn ns nS ns nV nv np np Group 2 : | | CHK Instruction | 40(4/3)+ | np (n-) nn ns nS ns nV nv np np Divide by Zero | 38(4/3)+ | nn nn ns nS ns nV nv np np TRAP instruction | 34(4/3) | nn ns nS ns nV nv np np TRAPV instruction | 34(5/3) | np ns nS ns nV nv np np NOTES: .for CHK, Divide by Zero, Illegal, Trap and TRAPV : .The numbers of clock periods, for the "trap" lines, include the times for all stacking, the vector fetch and the fetch of the first instruction of THE handler routine. .First are pushed on the stack the program counter high and low words then the status register. .for CHK and Divide by zero, you must add effective address calculation time to the period (according to instruction section above). ./RESET line indicates the time from when /RESET and /HALT are first sampled as negated to when instruction execution starts. For a subsequent external reset, asserting these signals for 10 clock cycles or longer is mandatory to initiate reset sequence. During these 10 clock cycles the CPU is in halted state (see below). However, an external reset signal that is asserted while the CPU is executing a reset instruction is ignored. Since the processor asserts the /RESET signal for 124 clock cycles during execution of a reset instruction, an external reset should assert /RESET for at least 132 clock periods. .For all these exceptions, there is a difference of 2 cycles between Data bus usage as obtained from USP4325121 and periods as written in M68000UM. There's no proven theory to explain this gap. ******************************************************************************* HALTED STATE ******************************************************************************* ------------------------------------------------------------------------------- | Periods | Data Bus Usage ----------------------+----------+--------------------------------------------- | ?(0/0) | (n-)* NOTES : .this state is entered when a major failure happens and can only be exited by reseting the CPU. Between these two events fit as many (n-) as necessary. |
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